The development of video encoding technology requires significant hardware resources for providing the high quality of video compression and performance. Motion Estimation is an important part of the encoding process.
The encoding features in High Efficiency Video Coding (HEVC) define selection of Prediction Units (PU) and a process of derivation the Motion Vectors (MV). There are two new features in Inter-HEVC: the powerful mode of merging Coding Units (CU), and representation of coding units as a tree. These features can improve the quality of coding but they require additional efforts and resources to provide it. The main approach to achieve best encoding is by recursive re-calculation of pixels (multi-pass execution).
This approach does not provide efficient hardware implementation because it produces multi-loop structures that restrict the depth of the calculation pipeline and increase the requirements to memory bandwidth: the data is loaded several times because of the cache size restriction.
The pipelines and parallelism are traditional ways of providing a high performance. The depth of the pipeline is defined by the following factors: prediction of current CU that depends on encoding results of the previous CU; and the cycles of recursive calculation, which can be replaced by a parallel calculation. The parallelism, however, requires extra hardware for implementation.
The restrictions of hardware resources define the balance between the parallel and sequential calculation. Some of the restrictions are the scalability of architecture and the capability to support the different memory size and memory organization.
Therefore, there is a need to provide high performance motion estimation combined with good quality and minimum hardware restrictions.